The present invention relates generally to the field of digital data communication, and more particularly to the field of detecting and decoding phase-encoded data from a digital serial bit stream.
In order to detect and decode serial data, data communication systems have used a clock recovery circuit (CRC) to generate a clock signal from the transmitted data because the systems do not transmit a separate clock signal. A CRC may, for example, detect both positive and negative transitions of the data to generate a clock signal at the fundamental frequency of the serial data.
This type of edge-detection CRC has some drawbacks. When the serial data is in non-return to zero (NRZ) format, consecutive ones and zeros do not provide edges for the CRC to detect. During these periods, the CRC must maintain a clock at a previously determined rate and avoid any drift in the recovered clock frequency.
Another problem arises from random jitter and noise error introduced into the transmitted data stream. As data rates increase, the ability of the CRC to maintain an accurate clock to allow the data recovery circuit to recover the received data becomes more difficult because the tolerances become tighter.
One way to increase data rates without a higher clock frequency is to encode the data differently, such as with phase-encoding. Although many conventional serial data systems encode data bits as high and low levels of a data signal, phase-encoding encodes data bits by adjusting a duty cycle of the signal. Unlike the traditional level coding, phase encoding represents data by duty cycle.
FIG. 1A shows a data signal with a 50/50 duty cycle, where the data signal is high 50% of the cycle and low 50% of the cycle. FIG. 1B shows an example of a data signal with eight duty cycles or phase positions. Each position represents one of eight values, or three bits of data. The phase positions are centered around the 50% duty cycle to minimize bandwidth. Thus, the phase positions cover a particular range of the duty cycle, equal to 50%.+-.X%. For example, if X is 25, then phase position 0 would have a 25/75 duty cycle and represent 000, and phase position 7 would have a 75/25 duty cycle and represent 111.
Although phase-encoding allows data to be sent at a higher rate than standard data encoding, the receiving circuit must still extract a clock signal from the data. Conventional decoders of phase-encoded data signals use a phase-locked loop to produce a clock signal. The decoder uses the clock signals from the phase-locked loop to sample and decode received phase-encoded data signals. These decoders, however, still suffer from jitter and noise that can affect the decoding of the phase-encoded data.
Therefore, a phase-encoded data decoder is needed to obtain decoded data reliably.